In a first conventional output control circuit of a semiconductor memory, an address in the semiconductor memory is designated by a row address strobe (RAS) signal and a column address strobe (CAS) signal, and output data is supplied only if the RAS signal and the CAS signal are both at a low level. In the output control circuit, an access time by the CAS signal is equal to the minimum pulse width of the CAS signal which is required for an output operation. A level of the CAS signal must become high to turn an output terminal into a high impedance state simultaneously with the supply of the output data. Therefore, there is no stable state for the output data if a pulse width of the CAS signal which is in active state is equal to the minimum pulse width thereof, so that there is no time to supply the output data to an external circuit. This tendency especially occurs when the memory is operated in a so called page mode. Therefore, an actual pulse width of the CAS signal for the supply of the output data is the sum of a stable level time of the output level and the minimum pulse width of an access.
In a second conventional output control circuit of a semiconductor memory, there is provided with an extended output in which the output data is maintained even after the CAS signal becomes inactive. In operation, after the output data is supplied from an accessed memory cell to the output circuit by turning the RAS signal and the CAS signal into low, the output data is maintained at the output circuit until either the CAS signal turns into low again to access another address of the semiconductor memory after once turning into high, or both the RAS signal and the CAS signal turns into high. Practically, the output data is maintained to be supplied during a predetermined time including a precharging time of the CAS signal, so that a cycle for the page mode operation can be minimum.
According to the first and second conventional output control circuits of a semiconductor memory, however, there are disadvantages as described below.
In the first conventional output control circuit of a semiconductor memory, a minimum cycle of output operation which is a pulse width of the CAS signal becomes long, because the actual pulse width of the CAS signal is the sum of a stable level time of the output level and the minimum pulse width of the access as described above.
In the second conventional output control circuit of a semiconductor memory, the output operation of the page mode can not be carried out if the structure of the memory is such that input and output terminals are connected common (defined as "I/O common structure" hereinafter), for the reason that a wrong writing operation may occur, because the output data is maintained to be supplied at the output circuit even when the input data begins to be supplied to the common by connected input terminal. Therefore, the page mode can not be carried out with the I/O common structure, so that the ordinary mode must be carried out. However, the ordinary mode operation takes more time to carry out one memory cycle compared to the page mode operation. For instance, if the access time from the RAS signal is 100 ns, one memory cycle of the ordinary mode operation may become 190 ns, while that of the page mode operation may become 90 ns, so that the page mode operation is preferred for high speed accessing.
On the other hand, the I/O common structure is necessary for high density packaging such as a module for surface packaging of semiconductor memories. In such a module as having nine semiconductor memories each having a capacity of 1 Mega bits, the number of terminals necessary for input/output operation in the I/O common structure is 24, that is the sum of 2 for power supply and ground, 3 for the RAS signal, the CAS signal and a write enable (WE) signal, 10 for address access signals, and 9 for input and output signals. On the other hand, the number of necessary terminals is 33 in a separate I/O structure where input terminals and output terminals are provided separately. Accordingly, the width of the module in the separate I/O structure becomes approximately 8.4 cm, which is 1.4 times larger than that in the I/O common structure which is approximately 6.1 cm, so that the I/O common structure is essential for getting a smaller sized device.